Digital Concurrent Error Detection Schemes Using A Verilog HDL Fault Simulator
This project is concerned with the development of a “Processor” incorporating CED (concurrent error detection) based upon the use of information redundancy(Elliott 1990) (such as the Hamming cod or mode-3 code). The project also makes use of Verilog-HDL to perform fault modelling and simulation in order to assess the effectiveness of the techniques. It is expected that a hardware prototype is developed for targeting to a FPGA with a view to demonstrating the concepts and circuits developed.
In recent years the utilization of FPGAs extent to systems in space, where the environment is unreliable. This utilization of FPGAs had tremendously increased due to its flexibility, programmability and high-performance capabilities. Systems like DSP, satellite, Mars Rover and reconfigurable radios functions with FPGA. Moreover there are different equipment’s that functions with FPGA are in use and still undeveloped.
One of the main advantages of FPGAs is its programmable nature. Because of this facility, it has short time-to-market when compared with ASICs. In addition to the above reason, this chip can be easily fabricate, alter and rectify for a designer in a short time. Also Programmable FPGAs help in testing and experimenting new designs, the revenant engineering cost are also reduced.
Here In this project, FPGAs are preferable because of its High performance than processors (McMurtrey 2006). Unlike processors, FPGAs uses dedicated hardware for processing logic and doesn’t require an operating system(Bisen 2010).It also contain thousands of reconfigurable gate array logic circuitry. Another notable difference when comparing CPLDs with FPGAs is the presence in most FPGAs of higher-level embedded functions (such as adders and multipliers) and embedded memories. This adders and multiplier blocks are important in this project because these are the basic function of ALU. Some FPGAs have the capability of partial re-configuration that lets one portion of the device be re-programmed while other portions continue running. (Bisen 2010)
3. Why I intend to do and the relevance
Even though FPFAs has the above mentioned advantages, they are highly affected by radiations(McMurtrey 2006). For example , the highly flexible nature of FPGAs allows the designer to reprogram the chip in the field itself, as well as to correct any post development errors .Remote upgrading is also possible in FPGAS so that different functions can be switched in and out from the base station and the cost is reduced. Since the program is sent to the space for a long period of time, by changing the device configuration, the same chip can work for different variety of functions. In this case the data that are send to the space have a great chance of getting error, which can alter the entire function of the device.
4. What I intent to do, brief summary of activities undertaken
By considering the above drawbacks, in this project a hardware prototype is developed for targeting to a FPGA which incorporate Information redundancy technique to make the system more reliable and efficient. Some authors(L 1986) had defined these technique of concurrent error detection on VLSI, in that case they had used a residue code over the VLSI design(Elliott 1990). All those design have the disadvantage that they can only detect the errors not correcting. In this design, the system has not only the ability to detect but also to correct the errors, through this its can bring the advantage of low implementation cost in the form of silicon area but the overall speed of the system could be sacrificed.
Some of the important activates includes detail study about different encoding/decoding schemes (Hamming code, mode 3), parity codes check-some codes and Berger codes is necessary. Since the implementation should be carried out using Xilinx application it is required to study about how to design FPGA in that. More over some history about FPGA, its basic concept, its advantages, languages used in FPGA and the importance of HDL should be taken in to consideration in this project.In this design ALU is the main part of system where the CED method is introduced, the aim is to develop 32 bit ALU which can process multiplication into it, to make the system more advance. The last but the most important activity is to programme a fault injection simulator. While simulating the hardware with the fault injector it will corrupt a logic gate or configuration bit and it will be evaluated whether the hardware can detect and correct the error.
5. How to proceed and the methods that should follow to attain the aim ?
The main part of this project is to design ALU and to introduce an error correction/detection scheme into that. Here in this design Hamming code technique are developed into a 32 bit ALU structure as shown in the figure, where it capable of not only detecting but also to correct the errors. The main reason for choosing hamming code is because of its ease of implementation and the checking elements are very small(Elliott 1990).
The schematic shown belowconsists of an information processing section and a parityprocessing section; a word size of 8 bits was chosen forthis implementation of the information section, thereforethe number of parity bits required for a SEC/DEDHamming code is 5.
6. Hamming code Error Detection/correction
Error detection code is a method of encoding the data bit with parity bits, so that the error can be detected .For example the simplest error detection code is the 1-bit code. In this code, a single parity bit is added to n data bits, which is 1 if the odd number of data bits are 1s,0 otherwise. SO that the total number of 1s in the parity checked bits, including parity bits, should always be even. Suppose if there is any error it will produce odd number of 1 bits in the word.
Hamming codes can also be used to correct single errors. Supose a code word X is transmitted, then the received wordis
,where E is the error vector. In this case if there is no error then E will be zero; else if there is a single error then E is a vector with exactly one 1 and the rest 0s. We check a received matrix by multiplying by the parity-check matrix.
The parity of the result for the addition of two numbersis given by
, are the parity bits generated from the carriesof the addition operation.
+ represents carry in. The carry out from column 8 is not used in the generation of
(Elliott 1990). Both
and depend on the information bits beingsupplied to the information ALU and so two Hammingencoders are required within the information processingsection of the datapath to generate the and signals; these are located within the Auxiliary ALU( ). The encoders along with the checking and correctinghardware constitute the two points of interactionbetween the information and parity sections of the datapath,otherwise both sections operate independently.
- The main functional objectives of this project is demonstrating and evaluating CED/CEC technique using FPGA. The other objectives of this project includes
- To analyse the important characteristics of various coding techniques that could be used for error control in a FPGA to make it reliable.
- To study different coding techniques (likeHamming codes andmode-3 code)and the various methods used for encoding and decoding of the codes to achieve efficient detection and correction of the errors.
- Analysis of the simulation results of the Hamming encoder and decoder using a Model sim.
- To create a Hardware prototype using FPGA, that can detect and correct errors in ALU using Verilog-HDL.
- Hardware prototype is developed using FPGA in order to demonstrate the concept of CED its correction and the circuit developed.
- To evaluate the speed of the hardware and the area overhead required after introducing CED/CEC techniques.
· FPGA kit
· Model Sim
Finished.....PLease leave your questions as comment............
If you need help in any programming section in verilog,, pplz contact
If you need help in any programming section in verilog,, pplz contact